1. Field of the Invention
The present invention relates to a dynamic semiconductor memory device and more specifically it relates to a semiconductor memory device which is suitable for high integration.
2. Description of the Prior Art
A dynamic semiconductor memory device has been widely known. FIG. 1 is a block diagram showing the whole structure of a conventional dynamic semiconductor memory device.
Referring to FIG. 1, the dynamic semiconductor memory device comprises an array including a plurality of memory cells constituting a memory portion, a X decoder and a Y decoder for selecting the address thereof and an input/output interface portion including a sense amplifier connected to an input/output buffer. The plurality of memory cells constituting the memory portion are connected to each of intersections of the word lines connected to the X decoder and the bit lines connected to the Y decoder structured in a matrix, thereby forming the said array.
The operation will be hereinafter described. In response to an externally applied row address signal and column address signal, that memory cell is selected which is at the intersection of one word line and one bit line, each of which is selected by the X decoder and the Y decoder and the information is read out or written into the memory cell through the input/output buffer and the input/output interface portion including the sense amplifier.
Generally, as a semiconductor memory device especially a dynamic semiconductor memory device comes to be more highly integrated, the area occupied by the memory cells, constituting the information storing portion, tends to be smaller. In order to secure as much capacitance as possible in a limited area, various types of memory cells have been proposed. For example, FIG. 2A shows a plan view of a conventional semiconductor memory device in which a fine aperture, which may be referred to as a trench region, is formed in a semiconductor substrate and the side wall thereof is used as a capacitor portion to provide sufficient capacitance (for example, Patent Publication Gazette 12739/1983). FIG. 2B is a cross sectional view taken along the line IIB--IIB of FIG. 2A.
FIG. 3A is a plan view showing a semiconductor memory device arranged to be suited for a folded bit line structure, FIG. 3B is a cross sectional view taken along the line IIIB--IIIB of FIG. 3A and FIGS. 4A to 4C are cross sectional views showing the manufacturing method of the semiconductor memory device.
Referring to the figures, trench regions 10 and 11 which are used to form capacitors for storing information-representing charge are formed on the main surface of a p.sup.+ substrate 1 each in a trench form and to be juxtaposed each other. A capacitor region is formed by an impurity doped layer 6a and a cell plate 4 with a capacitor insulating film 5 interposed therebetween. The two juxtaposed trench regions 10 and 11 are separated by a separating region 2, and below the separating region 2 an inversion preventing layer 3 is formed for preventing inversion. Drain and source regions 6b of transistors are formed by the sides of the trench regions 10 and 11 opposite to the separation region. Above a channel region which is between the source and drain regions 6b, word lines 8a to 8d are formed through a gate insulating film 12. These word lines 8a to 8d and the capacitor electrode 4 are covered with an oxide film 12 and the bit lines formed on the oxide film 12 are connected to the source regions 6b of the transistors through a contact hole 13. Meanwhile , in the plan views such as FIGS. 2A and 3A, the Al bit lines 7 are omitted.
In such semiconductor memory device as described above, a trench region is formed in a semiconductor substrate and the sides and the bottom thereof are used as a portion for storing electric charge representing information in order to substantially increase the area.
The method for manufacturing the above described conventional semiconductor memory device will be described with reference to FIGS. 4A to 4C. First, boron is ion implanted into that portion which is to be an element-separating region, so that a p.sup.+ type channel stop region 3 for separating elements is formed, and then a field oxide film 2 is formed (FIG. 4A). Then trench regions 10 and 11 are formed and by arsenic ion implantation, for example, a n.sup.+ type diffusion region 6a which is to be a charge storing region is formed (FIG. 4B). Next, a first polysilicon layer 4 which is to be a cell plate is formed and a silicon oxide film 12 is deposited thereon by, for example, a chemical vapor deposition (CVD) method and word lines 8a to 8d are formed by a second layer of polycrystalline silicon (FIG. 4C). Subsequently, a n.sup.+ diffusion layer 6b is formed and an insulating layer of for example phosphosilicate glass is formed. Thereafter a contact hole 9 is formed and an Al wire 7 is provided to obtain the conventional semiconductor memory device shown in FIGS. 3A and 3B.
The conventional semiconductor memory device is structured as described above. In order to realize higher integration, the space between the trenches 10 and 11 must be made narrower. In that case, the depletion layers generated on the opposing sides of the two juxtaposed trench regions 10 and 11 are connected to each other, causing a punch through which may damage the stored information. Detail information as to the short channel effect which causes the punch through is shown in, for example, "Subthreshold Conduction in MOSFET's", Geoffrey W. Taylor IEEE Transactions on Electron Devices, Vol. ED-26, No. 3, March 1978. Therefore, the conventional device can not always cope with the high integration.
Meanwhile, memory cells having two capacitors provided opposed to each other in a trench are disclosed in Japanese Patent Laying-Open Gazette No. 136256/1986 and in Japanese Patent Laying-Open Gazette No. 187263/1986. However, in the first mentioned prior art, the capacitance is not sufficient since the capacitor regions are formed only in the opposing areas, and in the second mentioned prior art, the manufacturing process is complicated.